Timing of operations in synchronous memory systems must tightly controlled if the memory system is to operate at optimum rates. Typically, timing of operations in synchronous systems is controlled by a memory controller operating in synchronization with edges of the master clock signal.
One problem that often occurs in such system arises from differences in propagation times of signals between a memory controller and memory devices controlled by the memory controller. Such timing differences may prevent the memory system from operating at its optimum rate. For example, the memory controller typically accepts new data from a memory device at leading clock edges (i.e., transitions of the master clock signal from low to high). If one of the memory devices outputs data at the specified clock edge propagation delays from the memory device to the memory controller may cause the data to arrive later than the specified clock edge. Therefore, the memory device outputs data a short time before the leading edge to compensate for propagation of delays.
One problem with such an approach is that propagation delays between the memory device and memory controller will depend upon the effective distance between the memory controller and the memory device, which depends upon the routing of signal lines connecting the memory controller to the memory device. Consequently, the data may still not arrive at the memory controller at the specified leading edge. Therefore, the memory controller must be prepared to accept the data for some time before and after the clock edge. To allow sufficient time to look for the data, the memory controller allots a larger than optimum time period for accepting the data. The overall speed of the memory system is limited correspondingly.